Static RAM (SRAM) is widely used as memory because it does not require the refresh necessary for DRAM (Dynamic Random Access Memory), and therefore, is capable of a fast operation accordingly.
On the other hand, in recent years, reduction in power consumption has been demanded. To realize a memory that consumes a small amount of electric power, it is necessary to reduce the operating voltage. DRAM has such a problem that if the operating voltage is reduced, the charged voltage of a capacitor provided in a memory cell is reduced, and therefore, the refresh operation needs to be performed frequently and it is difficult to reduce the power consumption. Because of this, SRAM is used in this field and reduction in power consumption is performed by reducing the operating voltage of SRAM.
A general SRAM has a plurality of word lines and a plurality of bit line pairs arranged so as to be perpendicular to each other, a plurality of static-type memory cells arranged in correspondence with crossing parts of the plurality of word lines and the plurality of bit line pairs, a plurality of column circuits provided in correspondence with each bit line pair, a row decoder, a column decoder, a word line driver, and a plurality of column switches. Each column circuit has a sense amplifier, a precharge circuit, an equalizer, a keeper circuit, a bit line pair separation switch, etc.
FIG. 1 is a diagram illustrating a configuration of a portion corresponding to one bit line pair of a general SRAM, i.e., a configuration corresponding to one column. Such circuits are provided in the number corresponding to the number of sets of bit line pairs.
As illustrated in FIG. 1, SRAM has a plurality (n+1) of word lines WL0 to WLn extending in parallel in the transverse direction, bit line pairs BL and BLX extending in parallel in the longitudinal direction, a plurality (n+1) of static-type memory cells C0 . . . Cn arranged in correspondence with crossing parts of the plurality of word lines and the bit line pairs, extended bit line pairs RD and RDX provided in correspondence with the bit line pair BL and BLX, transistors Tr and TrX forming connection circuits of the bit line pair BL and BLX and the extended bit line pair RD and RDX, a precharge circuit PC and a keeper circuit KP connected between the bit line pair BL and BLX, and a sense amplifier SA and an equalizer EQ connected between the extended bit line pair RD and RDX.
Each memory cell is a well known static-type memory cell having a flip-flop that interconnects the input and output of two inverters and two transistors provided between two connection nodes of the flip-flop and the bit line pair BL and BLX. The gates of the two transistors are connected to the corresponding word line WL and when a row selection signal is applied to the word line, the transistors are brought into conduction (turned on) and a state where the memory cell is connected to the bit line pair BL and BLX is brought about.
The bit line pair BL and BLX is very long and a number (N+1) of the memory cells C0 . . . Cn are connected thereto. The precharge circuit PC operates when a precharge signal turns to “Low (L)” and precharges the bit line pair BL and BLX to a “High (H)” level and does not operate when PRE is at H (off state). The keeper circuit KP maintains the bit line on the H side of the bit line pair BL and BLX at H. The transistors Tr and TrX are brought into conduction when a column signal COL is at L and enters a cutoff state when the column signal COL is at H. The sense amplifier SA enters the operating state when a sense amplifier activation signal SAE is at H and amplifies the high voltage side of the bit line pair BL and BLX to H and the low voltage side to L and does not operate when SAE is at L (off state). The equalizer EQ has the same configuration as that of the precharge circuit PC and short-circuits the bit line pair BL and BLX to bring them into the H state when an equalize signal EQD is at L and does not operate when the equalize signal EQD is at H (off state).
FIG. 2 is a time chart illustrating a read operation of the SRAM illustrated in FIG. 1. WL0 represents a row selection signal to be applied to the word line WL0 in the 0-th row, BL/BLX represents a voltage of the bit line pair BL and BLX, and RD/RDX represents a voltage of the extended bit line pair RD and RDX, respectively.
As described above, to the bit line pair BL and BLX, a number (n+1) of memory cells are connected and the row selection signal (active at H) is applied to one of the memory cells (here, in the 0-th row) and the two transistors are brought into conduction. In response to this, the voltage of one of the bit line pair BL and BLX drops according to data stored in the memory cell. At this time, the column signal COL is at L, the transistors Tr and TrX are in the conduction state, and the extended bit line pair RD and RDX also changes in the same manner as the bit line pair BL and BLX.
On the other hand, the precharge signal PRE and the equalize signal EQD are at H and the precharge circuit PC and the equalizer EQ enter the off state. The sense amplifier activation signal SAE is at L and the sense amplifier SA is in the off state.
When the voltage of one of the bit line pair BL and BLX and the extended bit line pair RD and RDX drops, the sense amplifier activation signal SAE changes to H. At this time, the row selection signal, the precharge signal PRE, and the column signal COL change to H and the equalize signal EQD is maintained at H.
In response to this, the bit line pair BL and BLX and the extended bit line pair RD and RDX are cut and separated and the voltage of the bit line pair BL and BLX changes to H by the precharge circuit PC. Because the row selection signal changes to L, the memory cell C0 is cut and separated from the bit line pair BL and BLX and maintains a state corresponding to the stored data.
The sense amplifier SA performs amplification so that the low voltage side of the extended bit line pair RD and RDX changes to L and the high voltage side changes to H or is maintained at H. The state where the extended bit line pair RD and RDX has changed is transmitted to an output circuit via the column switch. When outputting of the state of the extended bit line pair RD and RDX to the outside is completed, the sense amplifier activation signal SAE changes to L, the sense amplifier SA enters the off state, the equalize signal EQD changes to L, and the equalizer EQ changes the extended bit line pair RD and RDX to H.
As described above, both the bit line pair BL and BLX and the extended bit line pair RD and RDX turn to H, and a state where the next read may be performed is brought about.
The above is the read operation of a general SRAM.
It is inevitable for the transistor forming the memory cell to vary in the manufacturing process. Depending on the variations in the characteristics of N-channel transistors of two inverters, the amount of amplitude on the side where the bit line pair BL and BLX changes to L differs considerably. In other words, the speed at which one of the bit line pair BL and BLX changes to L differs.
In BL/BLX in FIG. 2, a illustrates a change when the N-channel transistor has excellent characteristics, b illustrates a change when the N-channel transistor has average characteristics, and c illustrates a change when the N-channel transistor has insufficient characteristics, respectively. In RD/RDX in FIG. 2, d illustrates a change when the N-channel transistor has excellent characteristics, e illustrates a change when the N-channel transistor has average characteristics, and f illustrates a change when the N-channel transistor has insufficient characteristics, respectively.
In order for the sense amplifier SA to correctly amplify the voltage on the side where the voltage of the extended bit line pair RD and RDX has dropped to L, it is necessary for a voltage difference between the extended bit line pair RD and RDX to be equal to or more than a predetermined amount. In other words, the voltage of the other of the extended bit line pair RD and RDX is at H, and therefore, it is necessary for the voltage of the other to be equal to or less than a predetermined value. There is no particular problem when the characteristics of the N-channel transistor are excellent, however, when the characteristics of the N-channel transistor are insufficient, it is not possible to change the sense amplifier activation signal SAE to H until the voltage of one of the extended bit line pair RD and RDX becomes a predetermined value or less. Because of this, the time for the voltage of one of the extended bit line pair RD and RDX to become a predetermined value or less determines the read rate.
As described above, in order to reduce power consumption, the operating voltage is reduced, however, the influence of the reduction in the read rate becomes more remarkable as the operating voltage is reduced. Because of this, it is difficult to reduce the operating voltage sufficiently while maintaining a predetermined operation speed.
Further, in SRAM, it is necessary to correctly read data stored in all the memory cells, and therefore, it is necessary to set the read rate in accordance with that of the memory cell of the lowest operation speed. If such a read rate is set, the transistor of the memory cell considerably changes the voltage of either of the bit line pair BL and BLX when reading data from a memory cell having a transistor of the average or excellent characteristics, in other words, the amount of amplitude is increased and power consumption is increased.
It is known to adopt a hierarchical structure of the bit line pair in order to reduce power consumption, however, amplification is performed so as to change the whole bit line pair of a large capacity with a large amplitude, and therefore, it is not possible to sufficiently reduce power consumption.